1. Field of the Invention
The present invention relates to load control devices for controlling the amount of power delivered to an electrical load. More specifically, the present invention relates to a drive circuit for a two-wire analog dimmer that includes a trigger circuit having a variable voltage threshold for preventing multiple attempted firings of a bidirectional semiconductor switch of the dimmer.
2. Description of the Related Art
A typical lighting dimmer is coupled between a source of alternating-current (AC) power (typically 50 or 60 Hz line voltage AC mains) and a lighting load. Standard dimmers use one or more semiconductor switches, such as triacs or field effect transistors (FETs), to control the amount of power delivered to the lighting load and thus the intensity of the light emitted by the load. The semiconductor switch is typically coupled in series between the source and the lighting load. Using a phase-control dimming technique, the dimmer renders the semiconductor switch conductive for a portion of each line half-cycle to provide power to the lighting load, and renders the semiconductor switch non-conductive for the other portion of the line half-cycle to disconnect power from the load.
Some dimmers are operable to control the intensity of low-voltage lighting loads, such as magnetic low-voltage (MLV) and electronic low-voltage (ELV) loads. Low-voltage loads are generally supplied with AC power via a step-down transformer, typically an isolation transformer. These step-down transformers step the voltage down to the low-voltage level, for example 12 to 24 volts, necessary to power the lamp or lamps. One problem with low-voltage lighting loads employing a transformer, specifically MLV loads, is that the transformers are susceptible to any direct-current (DC) components of the voltage provided across the transformer. A DC component in the voltage across the transformer can cause the transformer to generate acoustic noise and to saturate, increasing the temperature of the transformer and potentially damaging the transformer.
FIG. 1A is a simplified schematic diagram of a prior art magnetic low-voltage dimmer 10. The prior art dimmer 10 is coupled to an AC power source 12 via a HOT terminal 14 and an MLV load 16 via a DIMMED HOT terminal 18. The MLV load 16 includes a transformer 16A and a lamp load 16B. The dimmer 10 further comprises a triac 20, which is coupled in series electrical connection between the source 12 and the MLV load 16 and is operable to control the power delivered to the MLV load. The triac 20 has a gate (or control input) for rendering the triac conductive. Specifically, the triac 20 becomes conductive at a specific time each half-cycle and becomes non-conductive when a load current iL through the triac becomes substantially zero amps, i.e., at the end of the half-cycle. The amount of power delivered to the MLV load 16 is dependent upon the portion of each half-cycle that the triac 20 is conductive. An inductor L22 is coupled in series with the triac 20 for providing noise filtering of electromagnetic interference (EMI) at the HOT terminal 14 and DIMMED HOT terminal 18 of the dimmer 10.
A timing circuit 30 includes a resistor-capacitor (RC) circuit coupled in parallel electrical connection with the triac 20. Specifically, the timing circuit 30 comprises a potentiometer R32 and a capacitor C34. As the capacitor C34 charges and discharges each half-cycle of the AC power source 12, a voltage vC develops across the capacitor. A plot of the voltage vC across the capacitor C34 and the load current iL through the MLV load 16 is shown in FIG. 2. The capacitor C34 begins to charge at the beginning of each half-cycle (i.e., at time to in FIG. 2) at a rate dependent upon the resistance of the potentiometer R32 and the capacitance of the capacitor C34.
A diac 40, which is employed as a trigger device, is coupled in series between the timing circuit 30 and the gate of the triac 20. As soon as the voltage vC across the capacitor C34 exceeds a break-over voltage VBR (e.g., 30V) of the diac 40, the voltage across the diac quickly decreases in magnitude to a break-back voltage VBB. The quick change in voltage across the diac 40 and the capacitor C34 causes the diac to conduct a gate current iGATE to and from the gate of the triac 20. The gate current iGATE flows into the gate of the triac 20 during the positive half-cycles and out of the gate of the triac during the negative half-cycles.
FIG. 1B is a plot of the voltage-current characteristic of a typical diac. The values of the break-over voltage VBR and the break-back voltage VBB may differ slightly during the positive half-cycles and the negative half-cycles. Thus, the voltage-current characteristic of FIG. 1B shows the positive break-over voltage VBR+ and the positive break-back voltage VBB+ occurring during the positive half-cycles and the negative break-over voltage VBR− and the negative break-back voltage VBB− occurring during the negative half-cycles.
The charging time of the capacitor C34, i.e., the time constant of the RC circuit, varies in response to changes in the resistance of potentiometer R32 to alter the times at which the triac 20 begins conducting each half-cycle of the AC power source 12. The magnitude of the gate current iGATE is limited by a gate resistor R42. The gate current iGATE flows for a period of time TPULSE, which is determined by the capacitance of the capacitor C34, the difference between the break-over voltage VBR and the break-back voltage VBB of the diac 40, and the magnitude of the gate current iGATE. After the voltage vC across the capacitor C34 has exceeded the break-over voltage VBR of the diac 40 and the gate current iGATE has decreased to approximately zero amps, the voltage vC decreases by substantially the break-back voltage VBB of the diac 40.
While the gate current iGATE is flowing through the gate of the triac 20, the triac will begin to conduct current through the main load terminals, i.e., between the source 12 and the MLV load 16 (as shown at time t1 in FIG. 2). In order for the triac 20 to remain conductive after the gate current iGATE ceases to flow, the load current iL must exceed a predetermined latching current ILATCH of the triac before the gate current reaches zero amps. When the MLV lamp 16B is connected to the MLV transformer 16A, the load current iL through the main load terminals of the triac 20 is large enough such that the load current exceeds the latching current ILATCH of the triac. Thus, when the magnitude of the gate current iGATE falls to substantially zero amps after the gate current period TPULSE, the triac 20 remains conductive during the rest of the present half-cycle, i.e., until the load current iL through the main load terminals of the triac 20 nears zero amps (e.g., at time t2 in FIG. 2).
When the MLV lamp 16B is not connected to the MLV transformer 16A, i.e., the MLV transformer is unloaded, the MLV load 16 will have a larger inductance than when the MLV lamp is connected to the MLV transformer. The larger inductance L causes the load current iL through the main load terminals of the triac 20 to increase at a slower rate since the rate of change of the current through an inductor is inversely proportional to the inductance, i.e., diL/dt=vL/L (assuming the instantaneous voltage vL across the inductor remains constant). Accordingly, when the MLV lamp 16B is not connected, the load current iL may not rise fast enough to exceed the latching current of the triac 20, and the triac may stop conducting when the gate current iGATE falls to substantially zero amps.
FIG. 3 is a plot of the voltage vC across the capacitor C34 and the load current iL when the MLV transformer 16A is unloaded. After the voltage vC exceeds the break-over voltage VBR of the diac 40 (as shown by a peak A1), the load current iL begins to increase slowly (as shown by a peak B1). However, the load current iL does not reach the latching current ILATCH of the triac 20 before the gate current IGATE stops flowing, and thus the triac 10 does not latch on and the load current iL will begin to decrease. Because the triac 20 did not latch and becomes non-conductive, the voltage across the timing circuit 20 will be a substantially large voltage, i.e., substantially equal to the voltage of the AC power source 12, and the capacitor C34 will begin to charge again (as shown by a peak A2). Note that the load current iL does not have enough time to drop to zero amps. When the voltage vC exceeds the break-over voltage VBR for the second time in the present half-cycle, the gate current iGATE flows through the gate and the triac 20 will once again attempt to fire (as shown by a peak B2). Because the load current iL is not zero amps when the gate current iGATE begins to flow, the load current rises to a greater value than was achieved at peak B1. Nonetheless, the load current iL does not reach the latching current ILATCH, and thus the cycle repeats again (as shown by peaks A3 and B3). A similar, but complementary, situation occurs during the negative half-cycles. As shown in FIG. 3, the load current iL does not exceed the latching current ILATCH during any of the AC line half-cycles.
As the situation of FIG. 3 repeats for multiple half-cycles, i.e., the triac 20 attempts to repeatedly fire from one half-cycle to the next, the load current iL through the main load terminals of the triac may acquire either a positive or a negative DC component. Eventually, the DC component will cause the load current iL to exceed the latching current ILATCH during some half-cycles, e.g., the negative half-cycles as shown in FIG. 4. Thus, an asymmetric load current iL will flow through the MLV load 16, causing the MLV transformer 16A to generate acoustic noise and to overheat, which can potentially damage the MLV transformer.
Thus, there exists a need for an MLV dimmer that prevents the conduction of asymmetric currents through an MLV load when the MLV transformer is unloaded.